In conventional digital video communication systems data is made available to the customers' home television set at the request or demand of the customer. Customers select a channel and enter a code into a box (widely known as set top box) at home, and the program gets delivered. Such universal video-on-demand requires massive amounts of audio/video data multiplexing. This multiplexing is done as per the MPEG2 system standard (13818-1). Each set top box must receive data and then process it to produce a continuous-high-quality-audio/video-program.
In a Digital Video Broadcast (DVB) communication system audio/video data is transmitted in a transport stream. A decoding Time Stamp (DTS) and a Presentation Time Stamp (PTS) specify the time instance at which the packet should be decoded and presented, respectively. DTS and PTS are all referenced to the encoder's SYSTEM TIME CLOCK (STC) running at 27 MHz. Samples of the STC clock known as PCR values are transmitted in transport stream packet at regular time interval to the decoder and the reference time is reconstructed by means of these clock samples and a standard Phase Locked Loop (PLL).
FIG. 1 shows a conventional system setup for a clock recovery application. Here, an MPEG2 transport stream is fed to a DVB-T modulator via a transport stream packet injector. The modulator outputs a Coded Orthogonal Frequency Division Multiplexing (COFDM) signal, which is demodulated and detected by a front-end STB tuner. The output of the front-end tuner is a 188-byte transport stream packet, which contains both audio and video data. The STB back-end, which contains a CPU, decodes these transport stream packets and decoded audio/video data is fed to a television. For audio/video time synchronization, a 27 MHz VCXO is used in the STB back-end. In a practical scenario (DVB communication), the transport stream is received by an antenna and the antenna output is fed to an STB front-end.
FIG. 2 shows an existing system for clock recovery as disclosed by the publication entitled “A New Method of Clock Recovery in MPEG Decoders” by Hooman Hassanzadegan and Nima Sarshar, Iran. It shows the addition of a random value to the PCR value generated in the PCR generation block to indicate jitter. The simulation results show that the time spacing between every two consecutive PCRs is 0.1 second.
The drawback in the above mentioned system is that the computation involved for clock recovery requires a complex and high cost apparatus.
Correct clock recovery at the Set Top Box (STB) receiver side is essential for audio/video synchronization. However, there are several factors that lead to degradation in the clock recovery process. Some of these factors are:                The difference between the transmitter system clock frequency and the receiver STC frequency (Frequency of the voltage controlled oscillator);        Introduction of a significant amount of jitter by communication channel;        Delay introduced by the inner interleaving and de-interleaving blocks in the transmitter and receiver side (particularly in DVB-TERRESTRIAL transmission); and        In worst case channel conditions (such as ¼ guard interval, channel fading, low carrier-to-noise ratio etc.), arrival of Program Clock Reference (PCR) packets being delayed as the STB tuner front-end takes too much time to detect and demodulate the signal.        
In DVB-Terrestrial (DVB-T) communication, uncertain arrival of PCR packets at the receiver end causes serious problems in synchronization of receiver system clock with that of the transmitter.
The conventional methods available to overcome this aspect cannot reduce all the problems, specifically in worst case channel conditions. Problems such as color loss, jittery video, and audio dropouts still persist. Apart from this, existing methods have high computational overhead.
Thus, a need is felt for a clock recovery system that overcomes the clock recovery problems in the presence of PCR packet jitters in digital video communication.